The present invention relates generally to integrated circuits, and more specifically, to improved metal layer tip-to-tip short.
The back end of line (BEOL) is the second portion of integrated circuit fabrication where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer, i.e., the metallization layer. Common metals are copper interconnect and aluminum interconnect. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.
General steps of BEOL may include (silicidation of source/drain region usually considered as front end of line (FEOL) or middle of line (MOL). BEOL usually starts from material when copper (Cu) is used):
1. Silicidation of source and drain regions and the polysilicon region.
2. Adding a dielectric (first, lower layer is pre-metal dielectric (PMD) to isolate metal from silicon and polysilicon), and then chemical mechanical polishing/planarization processing it.
3. Make holes in PMD in order to make contacts in them.
4. Add metal layer 1.
5. Add a second dielectric (i.e., the intra-metal dielectric).
6. Make vias through dielectric to connect lower metal with higher metal, where the vias are filled by metal and steps 4-6 are repeated to form all metal layers.
7. Add final passivation layer to protect the microchip.